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<div class="header">
  <div class="summary">
<a href="#groups">API Reference</a> &#124;
<a href="#nested-classes">Data Structures</a> &#124;
<a href="#define-members">Macros</a> &#124;
<a href="#typedef-members">Typedefs</a> &#124;
<a href="#enum-members">Enumerations</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle"><div class="title">DMA (Direct Memory Access)<div class="ingroups"><a class="el" href="group__group__hal.html">HAL Drivers</a></div></div></div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p >High level interface for interacting with the direct memory access (DMA). </p>
<p >The DMA driver allows for initializing and configuring a DMA channel in order to trigger data transfers to and from memory and peripherals. The transfers occur independently of the CPU and can be triggered by software or hardware. Multiple channels can be active at the same time each with their own user-selectable priority and transfer characteristics.</p>
<h1><a class="anchor" id="section_dma_features"></a>
Features</h1>
<ul>
<li>CPU independent memory access</li>
<li>Access to memory and peripherals</li>
<li>Multiple independent channels</li>
<li>Configurable transer sizes and bursts</li>
<li>Configurable priorities</li>
<li>Event completion notification</li>
</ul>
<h1><a class="anchor" id="Usage"></a>
Flow</h1>
<p >The operational flow of the driver is listed below. This shows the basic order in which each of the functions would generally be called. While Initialize must always be first and Release always last, with care, the other functions can be reordered based on the implementation needs.</p><ol type="1">
<li>Initialize: <a class="el" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a> or <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a> or <a class="el" href="group__group__hal__dma.html#gabc98118d2b7664e261c37764abd77781">cyhal_dma_init_cfg</a></li>
<li>Configure: <a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a></li>
<li>Setup: <a class="el" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a>, <a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a>, <a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a>, or <a class="el" href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a></li>
<li>Enable: <a class="el" href="group__group__hal__dma.html#gaf115ccd96b17d81f93e084c17ed23675">cyhal_dma_enable</a></li>
<li>Trigger: <a class="el" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a> or via a hardware signal</li>
<li>Status/ReEnable (optional): <a class="el" href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">cyhal_dma_is_busy</a>, <a class="el" href="group__group__hal__dma.html#gaf115ccd96b17d81f93e084c17ed23675">cyhal_dma_enable</a></li>
<li>Cleanup (optional): <a class="el" href="group__group__hal__dma.html#gaad1fd14761365d64ba9ddbd236f17582">cyhal_dma_disable</a>, <a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a>, <a class="el" href="group__group__hal__dma.html#gaae942b5203638d1580b23e826bb04d53">cyhal_dma_disconnect_digital</a>, or <a class="el" href="group__group__hal__dma.html#gae6e7c942c2943ae20266611f8891002e">cyhal_dma_disable_output</a></li>
<li>Release (optional): <a class="el" href="group__group__hal__dma.html#ga8c1bf16caa5d53cb129e5544da1c8b21">cyhal_dma_free</a></li>
</ol>
<h1><a class="anchor" id="section_dma_quickstart"></a>
Quick Start</h1>
<p >See <a class="el" href="group__group__hal__dma.html#subsection_dma_snippet_1">Snippet 1: Simple DMA initialization and transfer</a> for a code snippet that sets up a DMA transfer to move memory from one location to another.</p>
<h1><a class="anchor" id="section_dma_snippets"></a>
Code snippets</h1>
<dl class="section note"><dt>Note</dt><dd>Error handling code has been intentionally left out of snippets to highlight API usage.</dd></dl>
<h2><a class="anchor" id="subsection_dma_snippet_1"></a>
Snippet 1: Simple DMA initialization and transfer</h2>
<p >The following snippet initializes a DMA channel and uses it to transfer a a single block of memory. The DMA channel is reserved by calling <a class="el" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>. It then needs to be configured with <a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a> and then the transfer is started with <a class="el" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a>.<br  />
 If the DMA channel is not needed anymore, it can be released by calling <a class="el" href="group__group__hal__dma.html#ga8c1bf16caa5d53cb129e5544da1c8b21">cyhal_dma_free</a></p>
<div class="fragment"><div class="line">    <a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>       rslt;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a>     dma;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> cfg =</div>
<div class="line">    {</div>
<div class="line">        .<a class="code hl_variable" href="group__group__hal__dma.html#addcfd22935f15ed7fd86990afb2d8fe5">src_addr</a>       = 0x8000000,               <span class="comment">// Start from address</span></div>
<div class="line">        .src_increment  = 1,                       <span class="comment">// Increment source by 1 word</span></div>
<div class="line">        .dst_addr       = 0x8001000,               <span class="comment">// Destination from address</span></div>
<div class="line">        .dst_increment  = 1,                       <span class="comment">// Increment destination by 1 word</span></div>
<div class="line">        .transfer_width = 32,                      <span class="comment">// 32 bit transfer</span></div>
<div class="line">        .length         = 0x10,                    <span class="comment">// Transfer 64 bytes (16 transfers of 4 bytes)</span></div>
<div class="line">        .burst_size     = 0,                       <span class="comment">// Transfer everything in a single burst</span></div>
<div class="line">        .action         = <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad">CYHAL_DMA_TRANSFER_FULL</a>, <span class="comment">// Notify when everything is done</span></div>
<div class="line">    };</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Allocate the DMA channel for use</span></div>
<div class="line">    rslt = <a class="code hl_define" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>(&amp;dma, <a class="code hl_define" href="group__group__hal__impl__dma.html#ga81946da56dd6ba8afd28f6056b1d779a">CYHAL_DMA_PRIORITY_DEFAULT</a>, <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a">CYHAL_DMA_DIRECTION_MEM2MEM</a>);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Configure the channel for the upcoming transfer</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>(&amp;dma, &amp;cfg);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Begin the transfer</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a>(&amp;dma);</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line">    <span class="comment">// If the DMA channel is no longer needed, it can be freed up for other uses</span></div>
<div class="line">    <span class="keywordflow">if</span> (!<a class="code hl_function" href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">cyhal_dma_is_busy</a>(&amp;dma))</div>
<div class="line">    {</div>
<div class="line">        <a class="code hl_function" href="group__group__hal__dma.html#ga8c1bf16caa5d53cb129e5544da1c8b21">cyhal_dma_free</a>(&amp;dma);</div>
<div class="line">    }</div>
<div class="ttc" id="agroup__group__hal__dma_html_addcfd22935f15ed7fd86990afb2d8fe5"><div class="ttname"><a href="group__group__hal__dma.html#addcfd22935f15ed7fd86990afb2d8fe5">cyhal_dma_cfg_t::src_addr</a></div><div class="ttdeci">uint32_t src_addr</div><div class="ttdoc">Source address. Some devices can apply special requirements for user data arrays. Please refer to imp...</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:265</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_ga6f962c164fedb088dbd2a48e21550fd0"><div class="ttname"><a href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">cyhal_dma_is_busy</a></div><div class="ttdeci">bool cyhal_dma_is_busy(cyhal_dma_t *obj)</div><div class="ttdoc">Checks if the transfer has been triggered, but not yet complete (eg: is pending, blocked or running)</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_ga8c1bf16caa5d53cb129e5544da1c8b21"><div class="ttname"><a href="group__group__hal__dma.html#ga8c1bf16caa5d53cb129e5544da1c8b21">cyhal_dma_free</a></div><div class="ttdeci">void cyhal_dma_free(cyhal_dma_t *obj)</div><div class="ttdoc">Free the DMA object.</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gab9c200507a8ee87b894150416e4f5dd1"><div class="ttname"><a href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a></div><div class="ttdeci">#define cyhal_dma_init(obj, priority, direction)</div><div class="ttdoc">Initialize the DMA peripheral.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:330</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gad39f32ac4fada8bc9e757df0a22fcce4"><div class="ttname"><a href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a></div><div class="ttdeci">cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)</div><div class="ttdoc">Setup the DMA channel behavior.</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gaf57a2b19848478b6604e09a3ecc3fbfc"><div class="ttname"><a href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a></div><div class="ttdeci">cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj)</div><div class="ttdoc">Initiates DMA channel transfer for specified DMA object.</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad"><div class="ttname"><a href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad">CYHAL_DMA_TRANSFER_FULL</a></div><div class="ttdeci">@ CYHAL_DMA_TRANSFER_FULL</div><div class="ttdoc">All bursts are triggered and a single CYHAL_DMA_TRANSFER_COMPLETE will occur at the end.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:251</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a"><div class="ttname"><a href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a">CYHAL_DMA_DIRECTION_MEM2MEM</a></div><div class="ttdeci">@ CYHAL_DMA_DIRECTION_MEM2MEM</div><div class="ttdoc">Memory to memory.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:184</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_structcyhal__dma__cfg__t"><div class="ttname"><a href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a></div><div class="ttdoc">Configuration of a DMA channel.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:264</div></div>
<div class="ttc" id="agroup__group__hal__impl__dma_html_ga81946da56dd6ba8afd28f6056b1d779a"><div class="ttname"><a href="group__group__hal__impl__dma.html#ga81946da56dd6ba8afd28f6056b1d779a">CYHAL_DMA_PRIORITY_DEFAULT</a></div><div class="ttdeci">#define CYHAL_DMA_PRIORITY_DEFAULT</div><div class="ttdoc">Default DMA channel priority.</div><div class="ttdef"><b>Definition:</b> cyhal_dma_impl.h:66</div></div>
<div class="ttc" id="agroup__group__hal__impl__hw__types_html_structcyhal__dma__t"><div class="ttname"><a href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a></div><div class="ttdoc">DMA object.</div><div class="ttdef"><b>Definition:</b> cyhal_hw_types.h:211</div></div>
<div class="ttc" id="agroup__group__result_html_gaca79700fcc701534ce61778a9bcf57d1"><div class="ttname"><a href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a></div><div class="ttdeci">uint32_t cy_rslt_t</div><div class="ttdoc">Provides the result of an operation as a structured bitfield.</div><div class="ttdef"><b>Definition:</b> cy_result.h:438</div></div>
</div><!-- fragment --><h2><a class="anchor" id="subsection_dma_snippet_2"></a>
Snippet 2: Configuring the DMA channel based on memory requirements</h2>
<p ><a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a> can be used after DMA initialization to handle a variety of memory layouts.</p>
<div class="fragment"><div class="line"><span class="preprocessor">    #define BUFFER_SIZE (32)</span></div>
<div class="line"><span class="preprocessor">    #define PERIPHERAL_FIFO_ADDR (0x4001000)</span></div>
<div class="line"> </div>
<div class="line">    <a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>   rslt;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> dma;</div>
<div class="line">    uint32_t    buffer[BUFFER_SIZE];</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Allocate the DMA channel for transfering from memory to a peripheral</span></div>
<div class="line">    rslt = <a class="code hl_define" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>(&amp;dma, <a class="code hl_define" href="group__group__hal__impl__dma.html#ga81946da56dd6ba8afd28f6056b1d779a">CYHAL_DMA_PRIORITY_DEFAULT</a>, <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665baef4c3c201a805bc17ea57d8dcfe49f49">CYHAL_DMA_DIRECTION_MEM2PERIPH</a>);</div>
<div class="line"> </div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> cfg =</div>
<div class="line">    {</div>
<div class="line">        .<a class="code hl_variable" href="group__group__hal__dma.html#addcfd22935f15ed7fd86990afb2d8fe5">src_addr</a>       = (uint32_t)buffer,        <span class="comment">// Start from address</span></div>
<div class="line">        .src_increment  = 1,                       <span class="comment">// Increment source by 1 word</span></div>
<div class="line">        .dst_addr       = PERIPHERAL_FIFO_ADDR,    <span class="comment">// Destination from address</span></div>
<div class="line">        .dst_increment  = 0,                       <span class="comment">// Don&#39;t increment the destination</span></div>
<div class="line">        .transfer_width = 32,                      <span class="comment">// 32 bit transfer</span></div>
<div class="line">        .length         = BUFFER_SIZE,             <span class="comment">// Transfer 64 bytes (16 transfers of 4 bytes)</span></div>
<div class="line">        .burst_size     = 0,                       <span class="comment">// Transfer everything in a single burst</span></div>
<div class="line">        .action         = <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad">CYHAL_DMA_TRANSFER_FULL</a>, <span class="comment">// Notify when everything is done</span></div>
<div class="line">    };</div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>(&amp;dma, &amp;cfg);</div>
<div class="ttc" id="agroup__group__hal__dma_html_gga430c1e3ddedade3b6f7ef1f8532e665baef4c3c201a805bc17ea57d8dcfe49f49"><div class="ttname"><a href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665baef4c3c201a805bc17ea57d8dcfe49f49">CYHAL_DMA_DIRECTION_MEM2PERIPH</a></div><div class="ttdeci">@ CYHAL_DMA_DIRECTION_MEM2PERIPH</div><div class="ttdoc">Memory to peripheral.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:185</div></div>
</div><!-- fragment --><h2><a class="anchor" id="subsection_dma_snippet_3"></a>
Snippet 3: Interrupts and retriggering DMA transfers</h2>
<p >DMA events like transfer complete or error events can be used to trigger a callback function. <br  />
 This snippet uses <a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a> to break the full transfer into multiple bursts. This allows higher priority items access to the memory bus if necessary while the DMA operation is still in progress. It then uses <a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event()</a> to enable the transfer complete event to trigger the callback function registered by <a class="el" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback()</a>.</p>
<div class="fragment"><div class="line"><span class="keywordtype">void</span> dma_event_callback(<span class="keywordtype">void</span>* callback_arg, <a class="code hl_enumeration" href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">cyhal_dma_event_t</a> event)</div>
<div class="line">{</div>
<div class="line">    CY_UNUSED_PARAMETER(event);</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a>* dma = (<a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a>*)callback_arg;</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Do work specific to each burst complete</span></div>
<div class="line"> </div>
<div class="line">    <span class="comment">// If all bursts are complete, start another</span></div>
<div class="line">    <span class="keywordflow">if</span> (!<a class="code hl_function" href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">cyhal_dma_is_busy</a>(dma))</div>
<div class="line">    {</div>
<div class="line">        <a class="code hl_function" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a>(dma);</div>
<div class="line">    }</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> snippet_cyhal_dma_events()</div>
<div class="line">{</div>
<div class="line">    <a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>       rslt;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a>     dma;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> cfg =</div>
<div class="line">    {</div>
<div class="line">        .<a class="code hl_variable" href="group__group__hal__dma.html#addcfd22935f15ed7fd86990afb2d8fe5">src_addr</a>       = 0x8000000,                <span class="comment">// Start from address</span></div>
<div class="line">        .src_increment  = 1,                        <span class="comment">// Increment source by 1 word</span></div>
<div class="line">        .dst_addr       = 0x8001000,                <span class="comment">// Destination from address</span></div>
<div class="line">        .dst_increment  = 1,                        <span class="comment">// Increment destination by 1 word</span></div>
<div class="line">        .transfer_width = 32,                       <span class="comment">// 32 bit transfer</span></div>
<div class="line">        .length         = 0x10,                     <span class="comment">// Transfer 64 bytes (16 transfers of 4 bytes)</span></div>
<div class="line">        .burst_size     = 4,                        <span class="comment">// Transfer 4 words a a time</span></div>
<div class="line">        .action         = <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e">CYHAL_DMA_TRANSFER_BURST</a>, <span class="comment">// Notify when each burst is done</span></div>
<div class="line">    };</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Allocate the DMA channel for use</span></div>
<div class="line">    rslt = <a class="code hl_define" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>(&amp;dma, <a class="code hl_define" href="group__group__hal__impl__dma.html#ga30998fd4febd3080e00922f969b08712">CYHAL_DMA_PRIORITY_LOW</a>, <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a">CYHAL_DMA_DIRECTION_MEM2MEM</a>);</div>
<div class="line">    CY_ASSERT(<a class="code hl_define" href="group__group__result.html#gaf58fac450d9fff4472f03ad68f6e546e">CY_RSLT_SUCCESS</a> == rslt);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Configure the channel for the upcoming transfer</span></div>
<div class="line">    <span class="keywordflow">if</span> (<a class="code hl_define" href="group__group__result.html#gaf58fac450d9fff4472f03ad68f6e546e">CY_RSLT_SUCCESS</a> == rslt)</div>
<div class="line">    {</div>
<div class="line">        rslt = <a class="code hl_function" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>(&amp;dma, &amp;cfg);</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Register an event callback handler and enable events</span></div>
<div class="line">    <span class="keywordflow">if</span> (<a class="code hl_define" href="group__group__result.html#gaf58fac450d9fff4472f03ad68f6e546e">CY_RSLT_SUCCESS</a> == rslt)</div>
<div class="line">    {</div>
<div class="line">        <a class="code hl_function" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a>(&amp;dma, &amp;dma_event_callback, &amp;dma);</div>
<div class="line">        <a class="code hl_function" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a>(&amp;dma, <a class="code hl_enumvalue" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a>, <a class="code hl_define" href="group__group__hal__impl__hw__types.html#gad822a466fc63847114add720ef84c83a">CYHAL_ISR_PRIORITY_DEFAULT</a>, <span class="keyword">true</span>);</div>
<div class="line"> </div>
<div class="line">        <span class="comment">// Begin the transfer</span></div>
<div class="line">        rslt = <a class="code hl_function" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a>(&amp;dma);</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="keywordflow">return</span> rslt;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="ttc" id="agroup__group__hal__dma_html_gacbccbcab79700c9e17bc47c525967876"><div class="ttname"><a href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a></div><div class="ttdeci">void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t callback, void *callback_arg)</div><div class="ttdoc">Register a DMA callback handler.</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gad41941e505b20be164c389925e7a25dc"><div class="ttname"><a href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a></div><div class="ttdeci">void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intr_priority, bool enable)</div><div class="ttdoc">Configure DMA event enablement.</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gad4507e9f3660b19e1ddc3085a96279e2"><div class="ttname"><a href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">cyhal_dma_event_t</a></div><div class="ttdeci">cyhal_dma_event_t</div><div class="ttdoc">Flags enum of DMA events.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:193</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e"><div class="ttname"><a href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e">CYHAL_DMA_TRANSFER_BURST</a></div><div class="ttdeci">@ CYHAL_DMA_TRANSFER_BURST</div><div class="ttdoc">A single burst is triggered and a CYHAL_DMA_TRANSFER_COMPLETE will occur after each burst.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:248</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73"><div class="ttname"><a href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a></div><div class="ttdeci">@ CYHAL_DMA_TRANSFER_COMPLETE</div><div class="ttdoc">Indicates that an individual transfer (burst or full) has completed based on the specified cyhal_dma_...</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:195</div></div>
<div class="ttc" id="agroup__group__hal__impl__dma_html_ga30998fd4febd3080e00922f969b08712"><div class="ttname"><a href="group__group__hal__impl__dma.html#ga30998fd4febd3080e00922f969b08712">CYHAL_DMA_PRIORITY_LOW</a></div><div class="ttdeci">#define CYHAL_DMA_PRIORITY_LOW</div><div class="ttdoc">Low DMA channel priority.</div><div class="ttdef"><b>Definition:</b> cyhal_dma_impl.h:72</div></div>
<div class="ttc" id="agroup__group__hal__impl__hw__types_html_gad822a466fc63847114add720ef84c83a"><div class="ttname"><a href="group__group__hal__impl__hw__types.html#gad822a466fc63847114add720ef84c83a">CYHAL_ISR_PRIORITY_DEFAULT</a></div><div class="ttdeci">#define CYHAL_ISR_PRIORITY_DEFAULT</div><div class="ttdoc">Priority that is applied by default to all drivers when initialized.</div><div class="ttdef"><b>Definition:</b> cyhal_hw_types.h:114</div></div>
<div class="ttc" id="agroup__group__result_html_gaf58fac450d9fff4472f03ad68f6e546e"><div class="ttname"><a href="group__group__result.html#gaf58fac450d9fff4472f03ad68f6e546e">CY_RSLT_SUCCESS</a></div><div class="ttdeci">#define CY_RSLT_SUCCESS</div><div class="ttdoc">cy_rslt_t return value indicating success</div><div class="ttdef"><b>Definition:</b> cy_result.h:465</div></div>
</div><!-- fragment --><h2><a class="anchor" id="subsection_dma_snippet_4"></a>
Snippet 4: Using hardware signals with DMA</h2>
<p >DMA operations can be initiated by a hardware signal, or initiate a hardware signal on completion. <br  />
This snippet shows how either can be done with a timer object. </p><dl class="section note"><dt>Note</dt><dd>Not all devices have the same internal connections. As a result, it may not be possible to setup connections exactly as shown in the snippet on your device.</dd></dl>
<p>In the first case, the DMA output signal (<a class="el" href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a>) is used so that when the DMA operation complets it in turn causes the timer to run. <br  />
NOTE: The <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a> can also be used insted of <a class="el" href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a> to enable the output. The advantage of using init_adv is it makes sure the DMA instance that is allocated is able to connected to the specified signal.</p>
<div class="fragment"><div class="line">    rslt = <a class="code hl_define" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>(&amp;dma, 1, <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba6bb2146283e064542427ddffc2fbe0d7">CYHAL_DMA_DIRECTION_PERIPH2PERIPH</a>);</div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>(&amp;dma, &amp;dma_config);</div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a>(&amp;dma, <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga68d247465101e4ca9d62d6c1ea2343c9aca155d063903043eadb915f4dfaa5069">CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS</a>, &amp;source);</div>
<div class="line"> </div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__timer.html#ga5458a719692e938b056150351b287967">cyhal_timer_connect_digital</a>(&amp;timer, source, <a class="code hl_enumvalue" href="group__group__hal__timer.html#ggadb5da20c0e7111025f4091339dd36fc4a39572bdfb86d6dadc6d9d08480590ec3">CYHAL_TIMER_INPUT_START</a>);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// starting the DMA transfers data and then starts the timer</span></div>
<div class="line">    <span class="comment">//CY_ASSERT(cyhal_timer_read(&amp;timer) == 0); // timer not started</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a>(&amp;dma);</div>
<div class="line">    <span class="keywordflow">while</span> (<a class="code hl_function" href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">cyhal_dma_is_busy</a>(&amp;dma))</div>
<div class="line">    {</div>
<div class="line">        <a class="code hl_function" href="group__group__hal__system.html#ga5f450769c1207d98134a9ced39adfdda">cyhal_system_delay_ms</a>(1);</div>
<div class="line">    }</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// DMA completed, and timer has started</span></div>
<div class="line">    <span class="comment">//CY_ASSERT(src == dst);</span></div>
<div class="line">    <span class="comment">//CY_ASSERT(cyhal_timer_read(&amp;timer) &gt; 0);</span></div>
<div class="ttc" id="agroup__group__hal__dma_html_ga49f5cc82d015e6798c7578fe5b837dd6"><div class="ttname"><a href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a></div><div class="ttdeci">cy_rslt_t cyhal_dma_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source)</div><div class="ttdoc">Enables the specified output signal from a DMA channel that is triggered when a transfer is completed...</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gga430c1e3ddedade3b6f7ef1f8532e665ba6bb2146283e064542427ddffc2fbe0d7"><div class="ttname"><a href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba6bb2146283e064542427ddffc2fbe0d7">CYHAL_DMA_DIRECTION_PERIPH2PERIPH</a></div><div class="ttdeci">@ CYHAL_DMA_DIRECTION_PERIPH2PERIPH</div><div class="ttdoc">Peripheral to peripheral.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:187</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gga68d247465101e4ca9d62d6c1ea2343c9aca155d063903043eadb915f4dfaa5069"><div class="ttname"><a href="group__group__hal__dma.html#gga68d247465101e4ca9d62d6c1ea2343c9aca155d063903043eadb915f4dfaa5069">CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS</a></div><div class="ttdeci">@ CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS</div><div class="ttdoc">Trigger an output when all elements are transferred.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:223</div></div>
<div class="ttc" id="agroup__group__hal__system_html_ga5f450769c1207d98134a9ced39adfdda"><div class="ttname"><a href="group__group__hal__system.html#ga5f450769c1207d98134a9ced39adfdda">cyhal_system_delay_ms</a></div><div class="ttdeci">cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds)</div><div class="ttdoc">Requests that the current operation delays for at least the specified length of time.</div></div>
<div class="ttc" id="agroup__group__hal__timer_html_ga5458a719692e938b056150351b287967"><div class="ttname"><a href="group__group__hal__timer.html#ga5458a719692e938b056150351b287967">cyhal_timer_connect_digital</a></div><div class="ttdeci">cy_rslt_t cyhal_timer_connect_digital(cyhal_timer_t *obj, cyhal_source_t source, cyhal_timer_input_t signal)</div><div class="ttdoc">Connects a source signal and configures and enables a timer event to be triggered from that signal.</div></div>
<div class="ttc" id="agroup__group__hal__timer_html_ggadb5da20c0e7111025f4091339dd36fc4a39572bdfb86d6dadc6d9d08480590ec3"><div class="ttname"><a href="group__group__hal__timer.html#ggadb5da20c0e7111025f4091339dd36fc4a39572bdfb86d6dadc6d9d08480590ec3">CYHAL_TIMER_INPUT_START</a></div><div class="ttdeci">@ CYHAL_TIMER_INPUT_START</div><div class="ttdoc">Start signal.</div><div class="ttdef"><b>Definition:</b> cyhal_timer.h:146</div></div>
</div><!-- fragment --><p >The second snippet shows how a timer overflow can be used to trigger a DMA operation. It uses <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a> to setup the connection, but <a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a> could be used instead; with the same note as above about ensuring a connection between instances.</p>
<div class="fragment"><div class="line">    rslt = <a class="code hl_function" href="group__group__hal__timer.html#ga0e7450df4a250d811d1ce60cb69285f8">cyhal_timer_enable_output</a>(&amp;timer, <a class="code hl_enumvalue" href="group__group__hal__timer.html#gga3b82fcbb7e540b55f1923f0cc4c77c30a46034ce48203bb1afe267c91a0f73e6e">CYHAL_TIMER_OUTPUT_OVERFLOW</a>, &amp;source);</div>
<div class="line"> </div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__dma.html#structcyhal__dma__src__t">cyhal_dma_src_t</a> dma_src =</div>
<div class="line">    {</div>
<div class="line">        .<a class="code hl_variable" href="group__group__hal__dma.html#a4458236b92f369fdde9715b8b6e45b3c">source</a> = source,</div>
<div class="line">        .input  = <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga5d4f22832c99a570fc99e9f3e64e46c0a97c5de1470fcdfd8c5c863ad8768bdd8">CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS</a>,</div>
<div class="line">    };</div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a>(&amp;dma, &amp;dma_src, NULL, NULL, 1, <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba1226b2af396731bd8b959c14924bb612">CYHAL_DMA_DIRECTION_PERIPH2MEM</a>);</div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>(&amp;dma, &amp;dma_config);</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line">    <span class="comment">//CY_ASSERT(src != dst);    // values do not match before DMA</span></div>
<div class="line">    <a class="code hl_function" href="group__group__hal__timer.html#gaff09b3ffee75893da00d0a7dae2d9cb2">cyhal_timer_start</a>(&amp;timer);  <span class="comment">// start the timer that will trigger DMA</span></div>
<div class="line">    <a class="code hl_function" href="group__group__hal__system.html#ga5f450769c1207d98134a9ced39adfdda">cyhal_system_delay_ms</a>(100); <span class="comment">// give plenty of time for timer and DMA to finish</span></div>
<div class="line">    <span class="comment">//CY_ASSERT(src == dst);    // values now match after DMA finishes</span></div>
<div class="ttc" id="agroup__group__hal__dma_html_a4458236b92f369fdde9715b8b6e45b3c"><div class="ttname"><a href="group__group__hal__dma.html#a4458236b92f369fdde9715b8b6e45b3c">cyhal_dma_src_t::source</a></div><div class="ttdeci">cyhal_source_t source</div><div class="ttdoc">Source of signal to DMA; obtained from another driver's cyhal_&lt;PERIPH&gt;_enable_output.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:281</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gac1ab5fd8128e928de6827c5469de598f"><div class="ttname"><a href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a></div><div class="ttdeci">cy_rslt_t cyhal_dma_init_adv(cyhal_dma_t *obj, cyhal_dma_src_t *src, cyhal_dma_dest_t *dest, cyhal_source_t *dest_source, uint8_t priority, cyhal_dma_direction_t direction)</div><div class="ttdoc">Initialize the DMA peripheral.</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gga430c1e3ddedade3b6f7ef1f8532e665ba1226b2af396731bd8b959c14924bb612"><div class="ttname"><a href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba1226b2af396731bd8b959c14924bb612">CYHAL_DMA_DIRECTION_PERIPH2MEM</a></div><div class="ttdeci">@ CYHAL_DMA_DIRECTION_PERIPH2MEM</div><div class="ttdoc">Peripheral to memory.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:186</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_gga5d4f22832c99a570fc99e9f3e64e46c0a97c5de1470fcdfd8c5c863ad8768bdd8"><div class="ttname"><a href="group__group__hal__dma.html#gga5d4f22832c99a570fc99e9f3e64e46c0a97c5de1470fcdfd8c5c863ad8768bdd8">CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS</a></div><div class="ttdeci">@ CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS</div><div class="ttdoc">Transfer all elements when an input signal is received.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:215</div></div>
<div class="ttc" id="agroup__group__hal__dma_html_structcyhal__dma__src__t"><div class="ttname"><a href="group__group__hal__dma.html#structcyhal__dma__src__t">cyhal_dma_src_t</a></div><div class="ttdoc">DMA input connection information to setup while initializing the driver.</div><div class="ttdef"><b>Definition:</b> cyhal_dma.h:280</div></div>
<div class="ttc" id="agroup__group__hal__timer_html_ga0e7450df4a250d811d1ce60cb69285f8"><div class="ttname"><a href="group__group__hal__timer.html#ga0e7450df4a250d811d1ce60cb69285f8">cyhal_timer_enable_output</a></div><div class="ttdeci">cy_rslt_t cyhal_timer_enable_output(cyhal_timer_t *obj, cyhal_timer_output_t signal, cyhal_source_t *source)</div><div class="ttdoc">Enables the specified output signal from a tcpwm that will be triggered when the corresponding event ...</div></div>
<div class="ttc" id="agroup__group__hal__timer_html_gaff09b3ffee75893da00d0a7dae2d9cb2"><div class="ttname"><a href="group__group__hal__timer.html#gaff09b3ffee75893da00d0a7dae2d9cb2">cyhal_timer_start</a></div><div class="ttdeci">cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj)</div><div class="ttdoc">Starts the timer/counter with the pre-set configuration from cyhal_timer_configure.</div></div>
<div class="ttc" id="agroup__group__hal__timer_html_gga3b82fcbb7e540b55f1923f0cc4c77c30a46034ce48203bb1afe267c91a0f73e6e"><div class="ttname"><a href="group__group__hal__timer.html#gga3b82fcbb7e540b55f1923f0cc4c77c30a46034ce48203bb1afe267c91a0f73e6e">CYHAL_TIMER_OUTPUT_OVERFLOW</a></div><div class="ttdeci">@ CYHAL_TIMER_OUTPUT_OVERFLOW</div><div class="ttdoc">Overflow signal.</div><div class="ttdef"><b>Definition:</b> cyhal_timer.h:156</div></div>
</div><!-- fragment --><h2><a class="anchor" id="subsection_dma_snippet_5"></a>
Snippet 5: DMA transfers with D-cache</h2>
<p >If CPU D-cache is enabled, DMA transfers must be handled using cache management API when dealing with cacheable memory in order to maintain CPU data cache coherency. Regarding the CPU data cache coherence with DMA, the general rules are, <br  />
</p><ul>
<li>Source and destination buffers must be cacheline aligned (__SCB_DCACHE_LINE_SIZE) <br  />
</li>
<li>D-cache of DMA descriptor and D-cache of source's buffers must be cleaned before a DMA transfer <br  />
</li>
<li>D-cache of destination buffer must be invalidated after a DMA transfer <br  />
</li>
</ul>
<p >The following snippet initializes a DMA channel and uses it to transfer a single block from one cacheable memory to another cacheable memory. Cleaning D-cache of DMA descriptor is done by calling <a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>. Cleaning D-cache of source's buffer and Invalidating D-cache of destination's buffer should be done explicitly.</p>
<p >Refer to <a class="el" href="md_source_hal_dcache.html#DCACHE_Management">DCACHE_Management</a> for more information.</p>
<div class="fragment"><div class="line"><span class="preprocessor">#define BUFFER_SIZE (32) </span><span class="comment">/* multiple of cache line size */</span><span class="preprocessor"></span></div>
<div class="line">CY_ALIGN(__SCB_DCACHE_LINE_SIZE) uint32_t tx_buffer[BUFFER_SIZE];</div>
<div class="line">CY_ALIGN(__SCB_DCACHE_LINE_SIZE) uint32_t rx_buffer[BUFFER_SIZE]; <span class="comment">/* Memory address should be</span></div>
<div class="line"><span class="comment">                                                                         cacheline-aligned */</span></div>
<div class="line"><span class="keywordtype">void</span> snippet_cyhal_dma_with_dcache()</div>
<div class="line">{</div>
<div class="line">    <a class="code hl_typedef" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>   rslt;</div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> dma;</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// Allocate the DMA channel for transfering from memory to memory</span></div>
<div class="line">    rslt = <a class="code hl_define" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>(&amp;dma, <a class="code hl_define" href="group__group__hal__impl__dma.html#ga81946da56dd6ba8afd28f6056b1d779a">CYHAL_DMA_PRIORITY_DEFAULT</a>, <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a">CYHAL_DMA_DIRECTION_MEM2MEM</a>);</div>
<div class="line"> </div>
<div class="line">    <a class="code hl_struct" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> cfg =</div>
<div class="line">    {</div>
<div class="line">        .<a class="code hl_variable" href="group__group__hal__dma.html#addcfd22935f15ed7fd86990afb2d8fe5">src_addr</a>       = (uint32_t)tx_buffer,     <span class="comment">// Start from address</span></div>
<div class="line">        .src_increment  = 1,                       <span class="comment">// Increment source by 1 word</span></div>
<div class="line">        .dst_addr       = (uint32_t)rx_buffer,     <span class="comment">// Destination from address</span></div>
<div class="line">        .dst_increment  = 1,                       <span class="comment">// Don&#39;t increment the destination</span></div>
<div class="line">        .transfer_width = 32,                      <span class="comment">// 32 bit transfer</span></div>
<div class="line">        .length         = BUFFER_SIZE,             <span class="comment">// Transfer 64 bytes (16 transfers of 4 bytes)</span></div>
<div class="line">        .burst_size     = 0,                       <span class="comment">// Transfer everything in a single burst</span></div>
<div class="line">        .action         = <a class="code hl_enumvalue" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad">CYHAL_DMA_TRANSFER_FULL</a>, <span class="comment">// Notify when everything is done</span></div>
<div class="line">    };</div>
<div class="line">    <span class="comment">/* cyhal_dma_configure will do clean dcache of DMA descriptor. */</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>(&amp;dma, &amp;cfg);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* Before enabling DMA channel, clean dcahe of tx_buffer. */</span></div>
<div class="line">    SCB_CleanDCache_by_Addr((<span class="keywordtype">void</span>*)tx_buffer, BUFFER_SIZE * <span class="keyword">sizeof</span>(uint32_t));</div>
<div class="line">    SCB_CleanDCache_by_Addr((<span class="keywordtype">void</span>*)rx_buffer, BUFFER_SIZE * <span class="keyword">sizeof</span>(uint32_t));  <span class="comment">/* This maybe</span></div>
<div class="line"><span class="comment">                                                                                   optional. */</span></div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gaf115ccd96b17d81f93e084c17ed23675">cyhal_dma_enable</a>(&amp;dma);</div>
<div class="line"> </div>
<div class="line">    rslt = <a class="code hl_function" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a>(&amp;dma);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* Before reading rx_buffer, invalidate dcache of rx_buffer. */</span></div>
<div class="line">    SCB_InvalidateDCache_by_Addr((<span class="keywordtype">void</span>*)rx_buffer, BUFFER_SIZE * <span class="keyword">sizeof</span>(uint32_t));</div>
<div class="ttc" id="agroup__group__hal__dma_html_gaf115ccd96b17d81f93e084c17ed23675"><div class="ttname"><a href="group__group__hal__dma.html#gaf115ccd96b17d81f93e084c17ed23675">cyhal_dma_enable</a></div><div class="ttdeci">cy_rslt_t cyhal_dma_enable(cyhal_dma_t *obj)</div><div class="ttdoc">Enable the DMA transfer so that it can start transferring data when triggered.</div></div>
</div><!-- fragment --> <table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="groups" name="groups"></a>
API Reference</h2></td></tr>
<tr class="memitem:group__group__hal__results__dma"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__results__dma.html">DMA HAL Results</a></td></tr>
<tr class="memdesc:group__group__hal__results__dma"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA specific return codes. <br /></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:structcyhal__dma__cfg__t"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a></td></tr>
<tr class="memdesc:structcyhal__dma__cfg__t"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration of a DMA channel.  <a href="group__group__hal__dma.html#structcyhal__dma__cfg__t">More...</a><br /></td></tr>
<tr class="separator:structcyhal__dma__cfg__t"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:structcyhal__dma__src__t"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#structcyhal__dma__src__t">cyhal_dma_src_t</a></td></tr>
<tr class="memdesc:structcyhal__dma__src__t"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA input connection information to setup while initializing the driver.  <a href="group__group__hal__dma.html#structcyhal__dma__src__t">More...</a><br /></td></tr>
<tr class="separator:structcyhal__dma__src__t"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:structcyhal__dma__dest__t"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#structcyhal__dma__dest__t">cyhal_dma_dest_t</a></td></tr>
<tr class="memdesc:structcyhal__dma__dest__t"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA output connection information to setup while initializing the driver.  <a href="group__group__hal__dma.html#structcyhal__dma__dest__t">More...</a><br /></td></tr>
<tr class="separator:structcyhal__dma__dest__t"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gab9c200507a8ee87b894150416e4f5dd1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">cyhal_dma_init</a>(obj,  priority,  direction)&#160;&#160;&#160;(<a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a>(obj, NULL, NULL, NULL, priority, direction))</td></tr>
<tr class="memdesc:gab9c200507a8ee87b894150416e4f5dd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the DMA peripheral.  <a href="group__group__hal__dma.html#gab9c200507a8ee87b894150416e4f5dd1">More...</a><br /></td></tr>
<tr class="separator:gab9c200507a8ee87b894150416e4f5dd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Typedefs</h2></td></tr>
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typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><b>cyhal_dma_event_callback_t</b>) (void *callback_arg, <a class="el" href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">cyhal_dma_event_t</a> event)</td></tr>
<tr class="memdesc:ga8d2fdb7ab4e9ba5367ef596ad42bbe3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Event handler for DMA interrupts. <br /></td></tr>
<tr class="separator:ga8d2fdb7ab4e9ba5367ef596ad42bbe3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Enumerations</h2></td></tr>
<tr class="memitem:ga430c1e3ddedade3b6f7ef1f8532e665b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga430c1e3ddedade3b6f7ef1f8532e665b">cyhal_dma_direction_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a">CYHAL_DMA_DIRECTION_MEM2MEM</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665baef4c3c201a805bc17ea57d8dcfe49f49">CYHAL_DMA_DIRECTION_MEM2PERIPH</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba1226b2af396731bd8b959c14924bb612">CYHAL_DMA_DIRECTION_PERIPH2MEM</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga430c1e3ddedade3b6f7ef1f8532e665ba6bb2146283e064542427ddffc2fbe0d7">CYHAL_DMA_DIRECTION_PERIPH2PERIPH</a>
<br />
 }</td></tr>
<tr class="memdesc:ga430c1e3ddedade3b6f7ef1f8532e665b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Direction for DMA transfers.  <a href="group__group__hal__dma.html#ga430c1e3ddedade3b6f7ef1f8532e665b">More...</a><br /></td></tr>
<tr class="separator:ga430c1e3ddedade3b6f7ef1f8532e665b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4507e9f3660b19e1ddc3085a96279e2"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">cyhal_dma_event_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2a31943df9f42ee4e594f2701f9daf16af">CYHAL_DMA_NO_INTR</a> = 0
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a> = 1 &lt;&lt; 0
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2a9832d2d5e5b138030ec765f9d1377730">CYHAL_DMA_DESCRIPTOR_COMPLETE</a> = 1 &lt;&lt; 1
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2aed1388898b5c44164b69c29226461c4f">CYHAL_DMA_SRC_BUS_ERROR</a> = 1 &lt;&lt; 2
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2a28e6e742cdc81f90dc1a0af854edcfa2">CYHAL_DMA_DST_BUS_ERROR</a> = 1 &lt;&lt; 3
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ac02b14f1884befe2fc3c736ca09b5063">CYHAL_DMA_SRC_MISAL</a> = 1 &lt;&lt; 4
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2aa975cfc15572bcde29d3b79771f3f69d">CYHAL_DMA_DST_MISAL</a> = 1 &lt;&lt; 5
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2a5d44bed82a7ab60351ccdc8be3ccac85">CYHAL_DMA_CURR_PTR_NULL</a> = 1 &lt;&lt; 6
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ac6197710bf44a105b69558913826465e">CYHAL_DMA_ACTIVE_CH_DISABLED</a> = 1 &lt;&lt; 7
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ad48347e72e87bd61c17fdab21128a0ef">CYHAL_DMA_DESCR_BUS_ERROR</a> = 1 &lt;&lt; 8
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2a642aeaae71d44d241fc1ed638e600a3c">CYHAL_DMA_GENERIC_ERROR</a> = 1 &lt;&lt; 9
<br />
 }</td></tr>
<tr class="memdesc:gad4507e9f3660b19e1ddc3085a96279e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flags enum of DMA events.  <a href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">More...</a><br /></td></tr>
<tr class="separator:gad4507e9f3660b19e1ddc3085a96279e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d4f22832c99a570fc99e9f3e64e46c0"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga5d4f22832c99a570fc99e9f3e64e46c0a7a41409940a58fbe674d52d63c50feb9">CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga5d4f22832c99a570fc99e9f3e64e46c0a694d225d972f01dce53f3a1aaf4a4627">CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga5d4f22832c99a570fc99e9f3e64e46c0a97c5de1470fcdfd8c5c863ad8768bdd8">CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS</a>
<br />
 }</td></tr>
<tr class="memdesc:ga5d4f22832c99a570fc99e9f3e64e46c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the transfer type to trigger when an input signal is received.  <a href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">More...</a><br /></td></tr>
<tr class="separator:ga5d4f22832c99a570fc99e9f3e64e46c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68d247465101e4ca9d62d6c1ea2343c9"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">cyhal_dma_output_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga68d247465101e4ca9d62d6c1ea2343c9a8d75b7bfccffd3c43e8e37d825642e0d">CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga68d247465101e4ca9d62d6c1ea2343c9a47f0861463a13062898fa526fce09e46">CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga68d247465101e4ca9d62d6c1ea2343c9aca155d063903043eadb915f4dfaa5069">CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS</a>
<br />
 }</td></tr>
<tr class="memdesc:ga68d247465101e4ca9d62d6c1ea2343c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the transfer completion event that triggers a signal output.  <a href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">More...</a><br /></td></tr>
<tr class="separator:ga68d247465101e4ca9d62d6c1ea2343c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga05291825b0a7c7b9a92373ec53342b7a"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga05291825b0a7c7b9a92373ec53342b7a">cyhal_dma_transfer_action_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e">CYHAL_DMA_TRANSFER_BURST</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad">CYHAL_DMA_TRANSFER_FULL</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa55e4b28b43c89e9125984fe81ea70f43">CYHAL_DMA_TRANSFER_BURST_DISABLE</a>
, <br />
&#160;&#160;<a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa2fa9971511772bcd18e1892eaad29b99">CYHAL_DMA_TRANSFER_FULL_DISABLE</a>
<br />
 }</td></tr>
<tr class="memdesc:ga05291825b0a7c7b9a92373ec53342b7a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This defines the behavior of the the channel when transfers are initiated.  <a href="group__group__hal__dma.html#ga05291825b0a7c7b9a92373ec53342b7a">More...</a><br /></td></tr>
<tr class="separator:ga05291825b0a7c7b9a92373ec53342b7a"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:gac1ab5fd8128e928de6827c5469de598f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, <a class="el" href="group__group__hal__dma.html#structcyhal__dma__src__t">cyhal_dma_src_t</a> *src, <a class="el" href="group__group__hal__dma.html#structcyhal__dma__dest__t">cyhal_dma_dest_t</a> *dest, <a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a> *dest_source, uint8_t priority, <a class="el" href="group__group__hal__dma.html#ga430c1e3ddedade3b6f7ef1f8532e665b">cyhal_dma_direction_t</a> direction)</td></tr>
<tr class="memdesc:gac1ab5fd8128e928de6827c5469de598f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the DMA peripheral.  <a href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">More...</a><br /></td></tr>
<tr class="separator:gac1ab5fd8128e928de6827c5469de598f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc98118d2b7664e261c37764abd77781"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gabc98118d2b7664e261c37764abd77781">cyhal_dma_init_cfg</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, const <a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__configurator__t">cyhal_dma_configurator_t</a> *cfg)</td></tr>
<tr class="memdesc:gabc98118d2b7664e261c37764abd77781"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the DMA peripheral using data provided by the configurator.  <a href="group__group__hal__dma.html#gabc98118d2b7664e261c37764abd77781">More...</a><br /></td></tr>
<tr class="separator:gabc98118d2b7664e261c37764abd77781"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c1bf16caa5d53cb129e5544da1c8b21"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga8c1bf16caa5d53cb129e5544da1c8b21">cyhal_dma_free</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj)</td></tr>
<tr class="memdesc:ga8c1bf16caa5d53cb129e5544da1c8b21"><td class="mdescLeft">&#160;</td><td class="mdescRight">Free the DMA object.  <a href="group__group__hal__dma.html#ga8c1bf16caa5d53cb129e5544da1c8b21">More...</a><br /></td></tr>
<tr class="separator:ga8c1bf16caa5d53cb129e5544da1c8b21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad39f32ac4fada8bc9e757df0a22fcce4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, const <a class="el" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> *cfg)</td></tr>
<tr class="memdesc:gad39f32ac4fada8bc9e757df0a22fcce4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Setup the DMA channel behavior.  <a href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">More...</a><br /></td></tr>
<tr class="separator:gad39f32ac4fada8bc9e757df0a22fcce4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf115ccd96b17d81f93e084c17ed23675"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gaf115ccd96b17d81f93e084c17ed23675">cyhal_dma_enable</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj)</td></tr>
<tr class="memdesc:gaf115ccd96b17d81f93e084c17ed23675"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the DMA transfer so that it can start transferring data when triggered.  <a href="group__group__hal__dma.html#gaf115ccd96b17d81f93e084c17ed23675">More...</a><br /></td></tr>
<tr class="separator:gaf115ccd96b17d81f93e084c17ed23675"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaad1fd14761365d64ba9ddbd236f17582"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gaad1fd14761365d64ba9ddbd236f17582">cyhal_dma_disable</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj)</td></tr>
<tr class="memdesc:gaad1fd14761365d64ba9ddbd236f17582"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the DMA transfer so that it does not continue to trigger.  <a href="group__group__hal__dma.html#gaad1fd14761365d64ba9ddbd236f17582">More...</a><br /></td></tr>
<tr class="separator:gaad1fd14761365d64ba9ddbd236f17582"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf57a2b19848478b6604e09a3ecc3fbfc"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj)</td></tr>
<tr class="memdesc:gaf57a2b19848478b6604e09a3ecc3fbfc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initiates DMA channel transfer for specified DMA object.  <a href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">More...</a><br /></td></tr>
<tr class="separator:gaf57a2b19848478b6604e09a3ecc3fbfc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f962c164fedb088dbd2a48e21550fd0"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">cyhal_dma_is_busy</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj)</td></tr>
<tr class="memdesc:ga6f962c164fedb088dbd2a48e21550fd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks if the transfer has been triggered, but not yet complete (eg: is pending, blocked or running)  <a href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">More...</a><br /></td></tr>
<tr class="separator:ga6f962c164fedb088dbd2a48e21550fd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbccbcab79700c9e17bc47c525967876"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, <a class="el" href="group__group__hal__dma.html#ga8d2fdb7ab4e9ba5367ef596ad42bbe3f">cyhal_dma_event_callback_t</a> callback, void *callback_arg)</td></tr>
<tr class="memdesc:gacbccbcab79700c9e17bc47c525967876"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a DMA callback handler.  <a href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">More...</a><br /></td></tr>
<tr class="separator:gacbccbcab79700c9e17bc47c525967876"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad41941e505b20be164c389925e7a25dc"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, <a class="el" href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">cyhal_dma_event_t</a> event, uint8_t intr_priority, bool enable)</td></tr>
<tr class="memdesc:gad41941e505b20be164c389925e7a25dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configure DMA event enablement.  <a href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">More...</a><br /></td></tr>
<tr class="separator:gad41941e505b20be164c389925e7a25dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2933aee1aa2f446f6aedf86ffee28040"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, <a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a> source, <a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a> input)</td></tr>
<tr class="memdesc:ga2933aee1aa2f446f6aedf86ffee28040"><td class="mdescLeft">&#160;</td><td class="mdescRight">Connects a source signal and enables the specified input to the DMA channel.  <a href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">More...</a><br /></td></tr>
<tr class="separator:ga2933aee1aa2f446f6aedf86ffee28040"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga49f5cc82d015e6798c7578fe5b837dd6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, <a class="el" href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">cyhal_dma_output_t</a> output, <a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a> *source)</td></tr>
<tr class="memdesc:ga49f5cc82d015e6798c7578fe5b837dd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the specified output signal from a DMA channel that is triggered when a transfer is completed.  <a href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">More...</a><br /></td></tr>
<tr class="separator:ga49f5cc82d015e6798c7578fe5b837dd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae942b5203638d1580b23e826bb04d53"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gaae942b5203638d1580b23e826bb04d53">cyhal_dma_disconnect_digital</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, <a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a> source, <a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a> input)</td></tr>
<tr class="memdesc:gaae942b5203638d1580b23e826bb04d53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disconnects a source signal and disables the specified input to the DMA channel.  <a href="group__group__hal__dma.html#gaae942b5203638d1580b23e826bb04d53">More...</a><br /></td></tr>
<tr class="separator:gaae942b5203638d1580b23e826bb04d53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae6e7c942c2943ae20266611f8891002e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__dma.html#gae6e7c942c2943ae20266611f8891002e">cyhal_dma_disable_output</a> (<a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *obj, <a class="el" href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">cyhal_dma_output_t</a> output)</td></tr>
<tr class="memdesc:gae6e7c942c2943ae20266611f8891002e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the specified output signal from a DMA channel.  <a href="group__group__hal__dma.html#gae6e7c942c2943ae20266611f8891002e">More...</a><br /></td></tr>
<tr class="separator:gae6e7c942c2943ae20266611f8891002e"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<hr/><h2 class="groupheader">Data Structure Documentation</h2>
<a name="structcyhal__dma__cfg__t" id="structcyhal__dma__cfg__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structcyhal__dma__cfg__t">&#9670;&nbsp;</a></span>cyhal_dma_cfg_t</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct cyhal_dma_cfg_t</td>
        </tr>
      </table>
</div><div class="memdoc">
<table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="addcfd22935f15ed7fd86990afb2d8fe5" name="addcfd22935f15ed7fd86990afb2d8fe5"></a>uint32_t</td>
<td class="fieldname">
src_addr</td>
<td class="fielddoc">
Source address. Some devices can apply special requirements for user data arrays. Please refer to implementation-specific documentation to see whether any limitations exist for used device. </td></tr>
<tr><td class="fieldtype">
<a id="a82383d2bf599937a55503e744b70a0bf" name="a82383d2bf599937a55503e744b70a0bf"></a>int16_t</td>
<td class="fieldname">
src_increment</td>
<td class="fielddoc">
Source address auto increment amount in multiples of transfer_width. </td></tr>
<tr><td class="fieldtype">
<a id="a4652fecb04594b84b09b07bee308e32a" name="a4652fecb04594b84b09b07bee308e32a"></a>uint32_t</td>
<td class="fieldname">
dst_addr</td>
<td class="fielddoc">
Destination address. Some devices can apply special requirements for user data arrays. Please refer to implementation-specific documentation to see whether any limitations exist for used device. </td></tr>
<tr><td class="fieldtype">
<a id="ac294f82b4a288c8d9ad084b3a6e9a26e" name="ac294f82b4a288c8d9ad084b3a6e9a26e"></a>int16_t</td>
<td class="fieldname">
dst_increment</td>
<td class="fielddoc">
Destination address auto increment amount in multiples of transfer_width. </td></tr>
<tr><td class="fieldtype">
<a id="ae5b6698dfc754dc0ca497842681ce7ef" name="ae5b6698dfc754dc0ca497842681ce7ef"></a>uint8_t</td>
<td class="fieldname">
transfer_width</td>
<td class="fielddoc">
Transfer width in bits. Valid values are: 8, 16, or 32. </td></tr>
<tr><td class="fieldtype">
<a id="aa7fbd97e22cee8fd0079fe27479f00c1" name="aa7fbd97e22cee8fd0079fe27479f00c1"></a>uint32_t</td>
<td class="fieldname">
length</td>
<td class="fielddoc">
Number of elements to be transferred in total. </td></tr>
<tr><td class="fieldtype">
<a id="ab9a976a59ce1acea9c281337c290d229" name="ab9a976a59ce1acea9c281337c290d229"></a>uint32_t</td>
<td class="fieldname">
burst_size</td>
<td class="fielddoc">
Number of elements to be transferred per trigger. If set to 0 every element is transferred, otherwise burst_size must evenly divide length. </td></tr>
<tr><td class="fieldtype">
<a id="a17a6575e0901cce49fdf8b7da8f2130d" name="a17a6575e0901cce49fdf8b7da8f2130d"></a><a class="el" href="group__group__hal__dma.html#ga05291825b0a7c7b9a92373ec53342b7a">cyhal_dma_transfer_action_t</a></td>
<td class="fieldname">
action</td>
<td class="fielddoc">
Sets the behavior of the channel when triggered (using start_transfer). Ignored if burst_size is not configured. </td></tr>
</table>

</div>
</div>
<a name="structcyhal__dma__src__t" id="structcyhal__dma__src__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structcyhal__dma__src__t">&#9670;&nbsp;</a></span>cyhal_dma_src_t</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">struct cyhal_dma_src_t</td>
        </tr>
      </table>
</div><div class="memdoc">
<table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="a4458236b92f369fdde9715b8b6e45b3c" name="a4458236b92f369fdde9715b8b6e45b3c"></a><a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a></td>
<td class="fieldname">
source</td>
<td class="fielddoc">
Source of signal to DMA; obtained from another driver's cyhal_&lt;PERIPH&gt;_enable_output. </td></tr>
<tr><td class="fieldtype">
<a id="a4a84836c06db798025e21943f253659f" name="a4a84836c06db798025e21943f253659f"></a><a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a></td>
<td class="fieldname">
input</td>
<td class="fielddoc">
DMA input signal to be driven. </td></tr>
</table>

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<a name="structcyhal__dma__dest__t" id="structcyhal__dma__dest__t"></a>
<h2 class="memtitle"><span class="permalink"><a href="#structcyhal__dma__dest__t">&#9670;&nbsp;</a></span>cyhal_dma_dest_t</h2>

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          <td class="memname">struct cyhal_dma_dest_t</td>
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<table class="fieldtable">
<tr><th colspan="3">Data Fields</th></tr>
<tr><td class="fieldtype">
<a id="a5fde47af76029eaba80edda37b16a065" name="a5fde47af76029eaba80edda37b16a065"></a><a class="el" href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">cyhal_dma_output_t</a></td>
<td class="fieldname">
output</td>
<td class="fielddoc">
Output signal of DMA. </td></tr>
<tr><td class="fieldtype">
<a id="a441e10ce6c695f05aaf2a6d128c46b81" name="a441e10ce6c695f05aaf2a6d128c46b81"></a><a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#gaa2df0778261ace69282e18e3ec39553c">cyhal_dest_t</a></td>
<td class="fieldname">
dest</td>
<td class="fielddoc">
Destination of DMA signal. </td></tr>
</table>

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<h2 class="groupheader">Macro Definition Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#gab9c200507a8ee87b894150416e4f5dd1">&#9670;&nbsp;</a></span>cyhal_dma_init</h2>

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          <td class="memname">#define cyhal_dma_init</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">obj, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">priority, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">direction&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(<a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a>(obj, NULL, NULL, NULL, priority, direction))</td>
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<p>Initialize the DMA peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[out]</td><td class="paramname">obj</td><td>Pointer to a DMA object. The caller must allocate the memory for this object but the init function will initialize its contents. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>The priority of this DMA operation relative to others. The number of priority levels which are supported is hardware dependent. All implementations define a <a class="el" href="group__group__hal__impl__dma.html#ga81946da56dd6ba8afd28f6056b1d779a" title="Default DMA channel priority.">CYHAL_DMA_PRIORITY_DEFAULT</a> constant which is always valid. If supported, implementations will also define <a class="el" href="group__group__hal__impl__dma.html#gaca50872208f80fb4625591afbaf79d70" title="High DMA channel priority.">CYHAL_DMA_PRIORITY_HIGH</a>, <a class="el" href="group__group__hal__impl__dma.html#ga0b9bf793bb1892836a901599c26fd698" title="Medium DMA channel priority.">CYHAL_DMA_PRIORITY_MEDIUM</a>, and <a class="el" href="group__group__hal__impl__dma.html#ga30998fd4febd3080e00922f969b08712" title="Low DMA channel priority.">CYHAL_DMA_PRIORITY_LOW</a>. The behavior of any other value is implementation defined. See the implementation-specific DMA documentation for more details. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">direction</td><td>The direction memory is copied </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the init request </dd></dl>

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</div>
<h2 class="groupheader">Enumeration Type Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#ga430c1e3ddedade3b6f7ef1f8532e665b">&#9670;&nbsp;</a></span>cyhal_dma_direction_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__dma.html#ga430c1e3ddedade3b6f7ef1f8532e665b">cyhal_dma_direction_t</a></td>
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<p>Direction for DMA transfers. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a" name="gga430c1e3ddedade3b6f7ef1f8532e665ba86dedc0ee3d9bf091e9f936040e2066a"></a>CYHAL_DMA_DIRECTION_MEM2MEM&#160;</td><td class="fielddoc"><p >Memory to memory. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga430c1e3ddedade3b6f7ef1f8532e665baef4c3c201a805bc17ea57d8dcfe49f49" name="gga430c1e3ddedade3b6f7ef1f8532e665baef4c3c201a805bc17ea57d8dcfe49f49"></a>CYHAL_DMA_DIRECTION_MEM2PERIPH&#160;</td><td class="fielddoc"><p >Memory to peripheral. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga430c1e3ddedade3b6f7ef1f8532e665ba1226b2af396731bd8b959c14924bb612" name="gga430c1e3ddedade3b6f7ef1f8532e665ba1226b2af396731bd8b959c14924bb612"></a>CYHAL_DMA_DIRECTION_PERIPH2MEM&#160;</td><td class="fielddoc"><p >Peripheral to memory. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga430c1e3ddedade3b6f7ef1f8532e665ba6bb2146283e064542427ddffc2fbe0d7" name="gga430c1e3ddedade3b6f7ef1f8532e665ba6bb2146283e064542427ddffc2fbe0d7"></a>CYHAL_DMA_DIRECTION_PERIPH2PERIPH&#160;</td><td class="fielddoc"><p >Peripheral to peripheral. </p>
</td></tr>
</table>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gad4507e9f3660b19e1ddc3085a96279e2">&#9670;&nbsp;</a></span>cyhal_dma_event_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">cyhal_dma_event_t</a></td>
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<p>Flags enum of DMA events. </p>
<p >Multiple events can be enabled via <a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a> and the callback from <a class="el" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a> will be run to notify. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2a31943df9f42ee4e594f2701f9daf16af" name="ggad4507e9f3660b19e1ddc3085a96279e2a31943df9f42ee4e594f2701f9daf16af"></a>CYHAL_DMA_NO_INTR&#160;</td><td class="fielddoc"><p >No interrupt. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73" name="ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73"></a>CYHAL_DMA_TRANSFER_COMPLETE&#160;</td><td class="fielddoc"><p >Indicates that an individual transfer (burst or full) has completed based on the specified <a class="el" href="group__group__hal__dma.html#ga05291825b0a7c7b9a92373ec53342b7a">cyhal_dma_transfer_action_t</a>. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2a9832d2d5e5b138030ec765f9d1377730" name="ggad4507e9f3660b19e1ddc3085a96279e2a9832d2d5e5b138030ec765f9d1377730"></a>CYHAL_DMA_DESCRIPTOR_COMPLETE&#160;</td><td class="fielddoc"><p >Indicates that the full transfer has completed. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2aed1388898b5c44164b69c29226461c4f" name="ggad4507e9f3660b19e1ddc3085a96279e2aed1388898b5c44164b69c29226461c4f"></a>CYHAL_DMA_SRC_BUS_ERROR&#160;</td><td class="fielddoc"><p >Indicates that there is a source bus error. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2a28e6e742cdc81f90dc1a0af854edcfa2" name="ggad4507e9f3660b19e1ddc3085a96279e2a28e6e742cdc81f90dc1a0af854edcfa2"></a>CYHAL_DMA_DST_BUS_ERROR&#160;</td><td class="fielddoc"><p >Indicates that there is a destination bus error. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2ac02b14f1884befe2fc3c736ca09b5063" name="ggad4507e9f3660b19e1ddc3085a96279e2ac02b14f1884befe2fc3c736ca09b5063"></a>CYHAL_DMA_SRC_MISAL&#160;</td><td class="fielddoc"><p >Indicates that the source address is not aligned. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2aa975cfc15572bcde29d3b79771f3f69d" name="ggad4507e9f3660b19e1ddc3085a96279e2aa975cfc15572bcde29d3b79771f3f69d"></a>CYHAL_DMA_DST_MISAL&#160;</td><td class="fielddoc"><p >Indicates that the destination address is not aligned. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2a5d44bed82a7ab60351ccdc8be3ccac85" name="ggad4507e9f3660b19e1ddc3085a96279e2a5d44bed82a7ab60351ccdc8be3ccac85"></a>CYHAL_DMA_CURR_PTR_NULL&#160;</td><td class="fielddoc"><p >Indicates that the current descriptor pointer is null. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2ac6197710bf44a105b69558913826465e" name="ggad4507e9f3660b19e1ddc3085a96279e2ac6197710bf44a105b69558913826465e"></a>CYHAL_DMA_ACTIVE_CH_DISABLED&#160;</td><td class="fielddoc"><p >Indicates that the active channel is disabled. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2ad48347e72e87bd61c17fdab21128a0ef" name="ggad4507e9f3660b19e1ddc3085a96279e2ad48347e72e87bd61c17fdab21128a0ef"></a>CYHAL_DMA_DESCR_BUS_ERROR&#160;</td><td class="fielddoc"><p >Indicates that there has been a descriptor bus error. </p>
</td></tr>
<tr><td class="fieldname"><a id="ggad4507e9f3660b19e1ddc3085a96279e2a642aeaae71d44d241fc1ed638e600a3c" name="ggad4507e9f3660b19e1ddc3085a96279e2a642aeaae71d44d241fc1ed638e600a3c"></a>CYHAL_DMA_GENERIC_ERROR&#160;</td><td class="fielddoc"><p >Indicates that there has been a generic error during the DMA transfer. </p>
</td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5d4f22832c99a570fc99e9f3e64e46c0">&#9670;&nbsp;</a></span>cyhal_dma_input_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a></td>
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<p>Specifies the transfer type to trigger when an input signal is received. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga5d4f22832c99a570fc99e9f3e64e46c0a7a41409940a58fbe674d52d63c50feb9" name="gga5d4f22832c99a570fc99e9f3e64e46c0a7a41409940a58fbe674d52d63c50feb9"></a>CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT&#160;</td><td class="fielddoc"><p >Transfer a single element when an input signal is received. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga5d4f22832c99a570fc99e9f3e64e46c0a694d225d972f01dce53f3a1aaf4a4627" name="gga5d4f22832c99a570fc99e9f3e64e46c0a694d225d972f01dce53f3a1aaf4a4627"></a>CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST&#160;</td><td class="fielddoc"><p >Transfer a single burst when an input signal is received. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga5d4f22832c99a570fc99e9f3e64e46c0a97c5de1470fcdfd8c5c863ad8768bdd8" name="gga5d4f22832c99a570fc99e9f3e64e46c0a97c5de1470fcdfd8c5c863ad8768bdd8"></a>CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS&#160;</td><td class="fielddoc"><p >Transfer all elements when an input signal is received. </p>
</td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#ga68d247465101e4ca9d62d6c1ea2343c9">&#9670;&nbsp;</a></span>cyhal_dma_output_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">cyhal_dma_output_t</a></td>
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<p>Specifies the transfer completion event that triggers a signal output. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga68d247465101e4ca9d62d6c1ea2343c9a8d75b7bfccffd3c43e8e37d825642e0d" name="gga68d247465101e4ca9d62d6c1ea2343c9a8d75b7bfccffd3c43e8e37d825642e0d"></a>CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT&#160;</td><td class="fielddoc"><p >Trigger an output when a single element is transferred. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga68d247465101e4ca9d62d6c1ea2343c9a47f0861463a13062898fa526fce09e46" name="gga68d247465101e4ca9d62d6c1ea2343c9a47f0861463a13062898fa526fce09e46"></a>CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST&#160;</td><td class="fielddoc"><p >Trigger an output when a single burst is transferred. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga68d247465101e4ca9d62d6c1ea2343c9aca155d063903043eadb915f4dfaa5069" name="gga68d247465101e4ca9d62d6c1ea2343c9aca155d063903043eadb915f4dfaa5069"></a>CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS&#160;</td><td class="fielddoc"><p >Trigger an output when all elements are transferred. </p>
</td></tr>
</table>

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<h2 class="memtitle"><span class="permalink"><a href="#ga05291825b0a7c7b9a92373ec53342b7a">&#9670;&nbsp;</a></span>cyhal_dma_transfer_action_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__hal__dma.html#ga05291825b0a7c7b9a92373ec53342b7a">cyhal_dma_transfer_action_t</a></td>
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<p>This defines the behavior of the the channel when transfers are initiated. </p>
<p >It can specify both how the transfer is broken up and what happens at the end of the transfer. If burst_size from <a class="el" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> is used, this specifies the granularity of operations that occur. Using <a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e">CYHAL_DMA_TRANSFER_BURST</a> or <a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa55e4b28b43c89e9125984fe81ea70f43">CYHAL_DMA_TRANSFER_BURST_DISABLE</a> means a single trigger will transfer a single burst (of burst_size) and raise the <a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a> interrupt. Using <a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad">CYHAL_DMA_TRANSFER_FULL</a> means a single trigger will transfer all bursts (total size length) and raise the <a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a> interrupt. If burst_size is not used, this has no impact and a single trigger will perform a complete transfer and raise a single interrupt at the end. When the transfer is complete, the channel can be left enabled, or automatically disabled. When left enabled (<a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e">CYHAL_DMA_TRANSFER_BURST</a> or <a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad">CYHAL_DMA_TRANSFER_FULL</a>) subsequent triggers will re-start the transfers. If the channel is diabled on completion (<a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa55e4b28b43c89e9125984fe81ea70f43">CYHAL_DMA_TRANSFER_BURST_DISABLE</a> or <a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa2fa9971511772bcd18e1892eaad29b99">CYHAL_DMA_TRANSFER_FULL_DISABLE</a>), <a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a> must be called to reconfigure the channel for future transfers.</p>
<dl class="section note"><dt>Note</dt><dd>When using <a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a> for a hardware input trigger, the <a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a> argument defines how much of the transfer is initiated at a time. This enum will still define when interrupts are raised. </dd></dl>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e" name="gga05291825b0a7c7b9a92373ec53342b7aa1d892969519c81dd0728bc5ea99c835e"></a>CYHAL_DMA_TRANSFER_BURST&#160;</td><td class="fielddoc"><p >A single burst is triggered and a <a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a> will occur after each burst. </p>
<p >The channel will be left enabled and can continue to be triggered. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad" name="gga05291825b0a7c7b9a92373ec53342b7aac422419b0c70b168a56a7bedc2bc2dad"></a>CYHAL_DMA_TRANSFER_FULL&#160;</td><td class="fielddoc"><p >All bursts are triggered and a single <a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a> will occur at the end. </p>
<p >The channel will be left enabled and can continue to be triggered. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga05291825b0a7c7b9a92373ec53342b7aa55e4b28b43c89e9125984fe81ea70f43" name="gga05291825b0a7c7b9a92373ec53342b7aa55e4b28b43c89e9125984fe81ea70f43"></a>CYHAL_DMA_TRANSFER_BURST_DISABLE&#160;</td><td class="fielddoc"><p >A single burst is triggered and a <a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a> will occur after each burst. </p>
<p >When all bursts are complete, the channel will be disabled. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga05291825b0a7c7b9a92373ec53342b7aa2fa9971511772bcd18e1892eaad29b99" name="gga05291825b0a7c7b9a92373ec53342b7aa2fa9971511772bcd18e1892eaad29b99"></a>CYHAL_DMA_TRANSFER_FULL_DISABLE&#160;</td><td class="fielddoc"><p >All bursts are triggered and a single <a class="el" href="group__group__hal__dma.html#ggad4507e9f3660b19e1ddc3085a96279e2ae5ed3faaed4b314d6b7115016e4c2e73">CYHAL_DMA_TRANSFER_COMPLETE</a> will occur at the end. </p>
<p >When complete, the channel will be disabled. </p>
</td></tr>
</table>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#gac1ab5fd8128e928de6827c5469de598f">&#9670;&nbsp;</a></span>cyhal_dma_init_adv()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_dma_init_adv </td>
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          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#structcyhal__dma__src__t">cyhal_dma_src_t</a> *&#160;</td>
          <td class="paramname"><em>src</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#structcyhal__dma__dest__t">cyhal_dma_dest_t</a> *&#160;</td>
          <td class="paramname"><em>dest</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a> *&#160;</td>
          <td class="paramname"><em>dest_source</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>priority</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#ga430c1e3ddedade3b6f7ef1f8532e665b">cyhal_dma_direction_t</a>&#160;</td>
          <td class="paramname"><em>direction</em>&#160;</td>
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          <td></td>
          <td>)</td>
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      </table>
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<p>Initialize the DMA peripheral. </p>
<p >If a source signal is provided for <code>src</code>, this will connect the provided signal to the DMA just as would be done by calling <a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a>. Similarly, if a destination target is provided for <code>dest</code> this will enable the specified output just as would be done by calling <a class="el" href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a>. </p><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[out]</td><td class="paramname">obj</td><td>Pointer to a DMA object. The caller must allocate the memory for this object but the init function will initialize its contents. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">src</td><td>An optional source signal to connect to the DMA </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">dest</td><td>An optional destination signal to drive from the DMA </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">dest_source</td><td>An optional pointer to user-allocated source signal object which will be initialized by enable_output. If <code>dest</code> is non-null, this must also be non-null. <code>dest_source</code> should be passed to (dis)connect_digital functions to (dis)connect the associated endpoints. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>The priority of this DMA operation relative to others. The number of priority levels which are supported is hardware dependent. All implementations define a <a class="el" href="group__group__hal__impl__dma.html#ga81946da56dd6ba8afd28f6056b1d779a" title="Default DMA channel priority.">CYHAL_DMA_PRIORITY_DEFAULT</a> constant which is always valid. If supported, implementations will also define <a class="el" href="group__group__hal__impl__dma.html#gaca50872208f80fb4625591afbaf79d70" title="High DMA channel priority.">CYHAL_DMA_PRIORITY_HIGH</a>, <a class="el" href="group__group__hal__impl__dma.html#ga0b9bf793bb1892836a901599c26fd698" title="Medium DMA channel priority.">CYHAL_DMA_PRIORITY_MEDIUM</a>, and <a class="el" href="group__group__hal__impl__dma.html#ga30998fd4febd3080e00922f969b08712" title="Low DMA channel priority.">CYHAL_DMA_PRIORITY_LOW</a>. The behavior of any other value is implementation defined. See the implementation-specific DMA documentation for more details. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">direction</td><td>The direction memory is copied </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the init request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gabc98118d2b7664e261c37764abd77781">&#9670;&nbsp;</a></span>cyhal_dma_init_cfg()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_dma_init_cfg </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">const <a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__configurator__t">cyhal_dma_configurator_t</a> *&#160;</td>
          <td class="paramname"><em>cfg</em>&#160;</td>
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<p>Initialize the DMA peripheral using data provided by the configurator. </p>
<dl class="section note"><dt>Note</dt><dd>Depending on what the configurator allows filling it, it is likely that at least the source and destination addresses of the transfer(s) still need to be setup.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[out]</td><td class="paramname">obj</td><td>Pointer to a DMA object. The caller must allocate the memory for this object but the init function will initialize its contents. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cfg</td><td>Configuration structure generated by a configurator. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the init request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8c1bf16caa5d53cb129e5544da1c8b21">&#9670;&nbsp;</a></span>cyhal_dma_free()</h2>

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          <td class="memname">void cyhal_dma_free </td>
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<p>Free the DMA object. </p>
<p >Freeing a DMA object while a transfer is in progress (<a class="el" href="group__group__hal__dma.html#ga6f962c164fedb088dbd2a48e21550fd0">cyhal_dma_is_busy</a>) is invalid.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gad39f32ac4fada8bc9e757df0a22fcce4">&#9670;&nbsp;</a></span>cyhal_dma_configure()</h2>

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          <td></td>
          <td class="paramtype">const <a class="el" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> *&#160;</td>
          <td class="paramname"><em>cfg</em>&#160;</td>
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<p>Setup the DMA channel behavior. </p>
<p >This will also enable the channel to allow it to be triggered. The transfer can be software triggered by calling <a class="el" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a> or by hardware. A hardware input signal is setup by <a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a> or <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a>. </p><dl class="section note"><dt>Note</dt><dd>If hardware triggers are used, any necessary event callback setup (<a class="el" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a> and <a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a>) should be done before calling this function to ensure the handlers are in place before the transfer can happen. </dd>
<dd>
The automatic enablement of the channel as part of this function is expected to change in a future update. This would only happen on a new major release (eg: 1.0 -&gt; 2.0). </dd>
<dd>
If the DMA was setup using <a class="el" href="group__group__hal__dma.html#gabc98118d2b7664e261c37764abd77781">cyhal_dma_init_cfg</a>, this function should not be used. </dd>
<dd>
If D-cache is enabled, this function cleans D-cache of DMA descriptor.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cfg</td><td>Configuration parameters for the transfer </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the configure request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf115ccd96b17d81f93e084c17ed23675">&#9670;&nbsp;</a></span>cyhal_dma_enable()</h2>

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<p>Enable the DMA transfer so that it can start transferring data when triggered. </p>
<p >A trigger is caused either by calling <a class="el" href="group__group__hal__dma.html#gaf57a2b19848478b6604e09a3ecc3fbfc">cyhal_dma_start_transfer</a> or by hardware as a result of a connection made in either <a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a> or <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a>. The DMA can be disabled by calling <a class="el" href="group__group__hal__dma.html#gaad1fd14761365d64ba9ddbd236f17582">cyhal_dma_disable</a> or by setting the <a class="el" href="group__group__hal__dma.html#structcyhal__dma__cfg__t">cyhal_dma_cfg_t</a> action to <a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa55e4b28b43c89e9125984fe81ea70f43">CYHAL_DMA_TRANSFER_BURST_DISABLE</a>, or <a class="el" href="group__group__hal__dma.html#gga05291825b0a7c7b9a92373ec53342b7aa2fa9971511772bcd18e1892eaad29b99">CYHAL_DMA_TRANSFER_FULL_DISABLE</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the enable request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaad1fd14761365d64ba9ddbd236f17582">&#9670;&nbsp;</a></span>cyhal_dma_disable()</h2>

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<p>Disable the DMA transfer so that it does not continue to trigger. </p>
<p >It can be reenabled by calling <a class="el" href="group__group__hal__dma.html#gaf115ccd96b17d81f93e084c17ed23675">cyhal_dma_enable</a> or <a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the enable request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf57a2b19848478b6604e09a3ecc3fbfc">&#9670;&nbsp;</a></span>cyhal_dma_start_transfer()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_dma_start_transfer </td>
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<p>Initiates DMA channel transfer for specified DMA object. </p>
<p >This should only be done after the channel has been configured (<a class="el" href="group__group__hal__dma.html#gad39f32ac4fada8bc9e757df0a22fcce4">cyhal_dma_configure</a>) and any necessary event callbacks setup (<a class="el" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a> <a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a>)</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the start_transfer request </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga6f962c164fedb088dbd2a48e21550fd0">&#9670;&nbsp;</a></span>cyhal_dma_is_busy()</h2>

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          <td class="memname">bool cyhal_dma_is_busy </td>
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<p>Checks if the transfer has been triggered, but not yet complete (eg: is pending, blocked or running) </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>True if DMA channel is busy </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gacbccbcab79700c9e17bc47c525967876">&#9670;&nbsp;</a></span>cyhal_dma_register_callback()</h2>

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          <td class="memname">void cyhal_dma_register_callback </td>
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          <td class="paramname"><em>obj</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#ga8d2fdb7ab4e9ba5367ef596ad42bbe3f">cyhal_dma_event_callback_t</a>&#160;</td>
          <td class="paramname"><em>callback</em>, </td>
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          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>callback_arg</em>&#160;</td>
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<p>Register a DMA callback handler. </p>
<p >This function will be called when one of the events enabled by <a class="el" href="group__group__hal__dma.html#gad41941e505b20be164c389925e7a25dc">cyhal_dma_enable_event</a> occurs.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">callback</td><td>The callback handler which will be invoked when an event triggers </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">callback_arg</td><td>Generic argument that will be provided to the callback when called </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gad41941e505b20be164c389925e7a25dc">&#9670;&nbsp;</a></span>cyhal_dma_enable_event()</h2>

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          <td class="memname">void cyhal_dma_enable_event </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#gad4507e9f3660b19e1ddc3085a96279e2">cyhal_dma_event_t</a>&#160;</td>
          <td class="paramname"><em>event</em>, </td>
        </tr>
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          <td class="paramkey"></td>
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          <td class="paramtype">uint8_t&#160;</td>
          <td class="paramname"><em>intr_priority</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Configure DMA event enablement. </p>
<p >When an enabled event occurs, the function specified by <a class="el" href="group__group__hal__dma.html#gacbccbcab79700c9e17bc47c525967876">cyhal_dma_register_callback</a> will be called.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">event</td><td>The DMA event type </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">intr_priority</td><td>The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>True to turn on interrupts, False to turn off </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2933aee1aa2f446f6aedf86ffee28040">&#9670;&nbsp;</a></span>cyhal_dma_connect_digital()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_dma_connect_digital </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a>&#160;</td>
          <td class="paramname"><em>source</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a>&#160;</td>
          <td class="paramname"><em>input</em>&#160;</td>
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<p>Connects a source signal and enables the specified input to the DMA channel. </p>
<p >This connection can also be setup automatically on initialization via <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a>. If the signal needs to be disconnected later, <a class="el" href="group__group__hal__dma.html#gaae942b5203638d1580b23e826bb04d53">cyhal_dma_disconnect_digital</a> can be used.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">source</td><td>Source signal obtained from another driver's cyhal_&lt;PERIPH&gt;_enable_output </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">input</td><td>Which input to enable </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the connection </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga49f5cc82d015e6798c7578fe5b837dd6">&#9670;&nbsp;</a></span>cyhal_dma_enable_output()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_dma_enable_output </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">cyhal_dma_output_t</a>&#160;</td>
          <td class="paramname"><em>output</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a> *&#160;</td>
          <td class="paramname"><em>source</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Enables the specified output signal from a DMA channel that is triggered when a transfer is completed. </p>
<p >This can also be setup automatically on initialization via <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a>. If the output is not needed in the future, <a class="el" href="group__group__hal__dma.html#gae6e7c942c2943ae20266611f8891002e">cyhal_dma_disable_output</a> can be used.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">output</td><td>Which event triggers the output </td></tr>
    <tr><td class="paramdir">[out]</td><td class="paramname">source</td><td>Pointer to user-allocated source signal object which will be initialized by enable_output. <code>source</code> should be passed to (dis)connect_digital functions to (dis)connect the associated endpoints. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the output enable </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaae942b5203638d1580b23e826bb04d53">&#9670;&nbsp;</a></span>cyhal_dma_disconnect_digital()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_dma_disconnect_digital </td>
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          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__impl__triggers__psoc6__01.html#ga96236d1368f920d28af90262e8b57046">cyhal_source_t</a>&#160;</td>
          <td class="paramname"><em>source</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#ga5d4f22832c99a570fc99e9f3e64e46c0">cyhal_dma_input_t</a>&#160;</td>
          <td class="paramname"><em>input</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Disconnects a source signal and disables the specified input to the DMA channel. </p>
<p >This removes the connection that was established by either <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a> or <a class="el" href="group__group__hal__dma.html#ga2933aee1aa2f446f6aedf86ffee28040">cyhal_dma_connect_digital</a>.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">source</td><td>Source signal from cyhal_&lt;PERIPH&gt;_enable_output to disable </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">input</td><td>Which input to disable </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the disconnect </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gae6e7c942c2943ae20266611f8891002e">&#9670;&nbsp;</a></span>cyhal_dma_disable_output()</h2>

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          <td class="memname"><a class="el" href="group__group__result.html#gaca79700fcc701534ce61778a9bcf57d1">cy_rslt_t</a> cyhal_dma_disable_output </td>
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          <td class="paramtype"><a class="el" href="group__group__hal__impl__hw__types.html#structcyhal__dma__t">cyhal_dma_t</a> *&#160;</td>
          <td class="paramname"><em>obj</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__hal__dma.html#ga68d247465101e4ca9d62d6c1ea2343c9">cyhal_dma_output_t</a>&#160;</td>
          <td class="paramname"><em>output</em>&#160;</td>
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          <td></td><td></td>
        </tr>
      </table>
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<p>Disables the specified output signal from a DMA channel. </p>
<p >This turns off the signal that was enabled by either <a class="el" href="group__group__hal__dma.html#gac1ab5fd8128e928de6827c5469de598f">cyhal_dma_init_adv</a> or <a class="el" href="group__group__hal__dma.html#ga49f5cc82d015e6798c7578fe5b837dd6">cyhal_dma_enable_output</a>. It is recommended that the signal is disconnected (cyhal_&lt;PERIPH&gt;_disconnect_digital) from anything it might be driving before being disabled.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">obj</td><td>The DMA object </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">output</td><td>Which output to disable </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The status of the disablement </dd></dl>

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